The present invention relates to a semiconductor device having a metal insulator metal (MIM) capacitor on the same level with a dual damascene Cu line.
A passive component having a capacitor is an integral part of many logic devices. This capacitor includes a decoupling capacitor of a MPU (Microprocessing Unit) device, a coupling and bypass capacitor for impedance matching between respective blocks in a SOC (System On a Chip) device and an RF device, and a capacitor array in an analogue-to-digital converter or a digital-to-analogue converter.
The related art obtains this capacitor by utilizing a junction capacitor having a silicon junction. Also, a MIM capacitor of Al/SiN/Al which uses a Plasma Enhanced Chemical Vapor Deposition (PECVD) SiN film as a dielectric film has been used in a general Al line technique.
However, a capacitor having a large capacity has been needed to increase the operation frequency and the number of bits of a converter.
For example, in the case of a Central Processing Unit (CPU) operating at 1 GHz, a capacitor capacity of 400 nF is needed for decoupling. Conventionally, an obtainable capacitance is 34.5 nF/mm2 if an average thickness (Toxeq) of a dielectric film is 1 nm. As a result, an area of 11.6 mm2 is finally needed for a capacitance of 400 nF.
If a dielectric ratio of a conventionally used PECVD SiN of 1000 xc3x85 is 7, an approximate Toxeq is 56 nm and a capacitance is 0.62 nF/mm2. Therefore, a capacitor of 645 mm2 area has to be fabricated, and this is a result that is not available in semiconductor chip fabrication.
There is a general tendency that metal line technology of logic devices is moving from Al to Cu. As a result of this technology shift, an insulating film MIM capacitor with a high dielectric ratio for large capacitance is needed. Realization of this type of MIM capacitor in a dual damascene Cu line process is currently viewed as an important research and development goal of logic device manufacturers.
Accordingly, a related art semiconductor device has the following problems.
In the conventional dual damascene line process and the capacitor forming process, it is complicated to fabricate a MIM capacitor having a high dielectric constant and a three-dimensional structure while maintaining the dual damascene patterning process.
The invention, in part, provides a semiconductor device and a method for fabricating the same that substantially solves one or more problems due to limitations and disadvantages of the related art.
The invention, in part, provides a semiconductor device and a method for fabricating the same which simplifies process steps and forms a MIM capacitor on the same level with a dual damascene Cu line.
The invention, in part, pertains to a semiconductor device that includes a first insulating interlayer on a substrate with a plurality of first contact holes, a plurality of first metal lines formed in the first contact holes, second and third insulating interlayers sequentially formed on the substrate including the first metal lines, second and third contact holes formed in the second insulating interlayer to expose some region of the first metal lines, and a trench formed in the third insulating interlayer to correspond to the second and third contact holes respectively. A first barrier metal film, a lower electrode of a capacitor, a dielectric film, and an upper electrode of a capacitor are sequentially formed in the second contact hole and the trench above the second contact hole. Second barrier metal films are respectively formed over the upper electrode of the capacitor of the second contact hole and the trench above the third contact hole. Second metal lines are respectively formed over the second contact hole, the third contact hole and the second barrier metal film to fill the trench.
The invention, in part, pertains to a diffusion barrier film formed over the first insulating interlayer. The semiconductor device can further have an etching stopper formed over the second insulating interlayer. A hard mask can be formed over the third insulating interlayer. Also, each trench above the second and third contact holes can have a greater width than widths of the second and third contact holes. Also the second contact hole, the trench above the second contact hole, the third contact hole, and the trench above the third contact hole can be respectively formed in a dual damascene structure. Preferably, the first and second metal lines are formed of Cu. In an additional embodiment, the second metal line is formed by combining a seed Cu film with an electroplated Cu film by a chemical and mechanical deposition or by combining a seed Cu film with an electroplated Cu film by an electroless method. In the device, the capacitor is preferably in a same level as the second metal lines.
In another preferred embodiment of the invention, a method for fabricating a semiconductor device includes the steps of: providing a substrate; forming a first insulating interlayer having a plurality of first contact holes over the substrate; forming a plurality of first metal lines in the first contact holes; sequentially forming second and third insulating interlayers over the first insulating interlayer; forming a plurality of first trenches on the third insulating interlayer so that at least one of the first trenches corresponds to the first metal lines; forming a first via hole over the second insulating interlayer below the first trenches corresponding to the first metal lines; sequentially forming a first barrier metal film, a first conductive layer, an insulating film, and a second conductive layer over the third insulating interlayer including the first via hole and the first trenches to expose a region of the third insulating interlayer; forming a plurality of second trenches in the exposed third insulating interlayer so that at least one of the second trenches corresponds to the first metal lines; forming a second via hole in the second insulating interlayer below the second trenches corresponding to the first metal lines; forming a second barrier metal film and a third conductive layer on the whole surface; forming a first barrier metal film and a capacitor in the first via hole and the first trench by a polishing process; and forming a second metal line in the second via hole and the second trench to have a same level with the capacitor.
The invention, in part, pertains to the first and the second metal lines being preferably formed of Cu, and the first and second barrier metal films are preferably formed by at least one of Cu, Ta, TaN, TiN, WN, TaC, WC, TiSiN, or TaSiN. Further, the first and the second conductive layers are preferably formed of at least one of Pt, Ru, Ir, or W, and the insulating film is preferably formed of at least one of a Ta oxide, a Baxe2x80x94Srxe2x80x94Ti oxide, a Zr oxide, a HF oxide, a Pbxe2x80x94Znxe2x80x94Ti oxide or a Srxe2x80x94Bixe2x80x94Ta oxide. Also, the first and second barrier metal films, the first and second conductive layers, and the insulating film are preferably formed by a PVD (Physical Vapor Deposition) method, a CVD (Chemical Vapor Deposition) method, or an ALD (Atomic Layer Deposition) method.
The method of the invention, in part, preferably has the steps of degassing under a high vacuum after putting a wafer in a barrier metal deposition apparatus, the degassing being performed before respectively forming the first and second barrier metal films; and cleaning using an argon sputter cleaning or a reactive cleaning using a plasma including H in a form of H2 and/or NH3. The third conductive layer can be formed from a Cu film, wherein the third conductive layer is formed by at least one of combining a seed Cu film with an electroplated Cu film by a PVD or CVD, or by combining the seed Cu film with the electroplated Cu film by an electroless Cu deposition.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.